Semiconductor chips are typically manufactured en masse in so called wafers. Each such wafer is made of a semiconductor material and typically is four to twelve inches in diameter. Each wafer typically contains a plurality of identical chips each connected and adjacent one another, but separated by portions of the wafer called scribe lines. The scribe lines do not contain devices which are required in the finished chips. Eventually, such individual chips are separated (or xe2x80x9cdicedxe2x80x9d) from one another for packaging and/or electrical connection to other chips. Prior to such further processing and connection, however, such chips need to be tested in order to determine which chips are defective so that further expense in processing does not occur on such defective chips. Such testing is typically called xe2x80x9cprobing.xe2x80x9d This testing may be accomplished by testing a single chip or multiple chips in defined rows on the wafer, and then repeating the testing operation with other chips or rows. Alternatively, the chips may be separated from one another first and then tested individually. Typically, probe contacts are abutted against (and preferably gently scrubbed or scraped against) respective chip contacts so that the chip circuitry may be tested. The process of testing one chip or a few chips at a time is slow and hence costly. Recently, simultaneous testing of a full undiced wafer has been discussed and is being tried by several manufacturers.
When probing chips or wafers, it is important to have a planar set of probe contacts so that each probe contact can make simultaneous electrical contact to a respective chip contact. It is also important to have the contacts on the wafer coplanar. Typically, if the tips of the probe contacts do not lie in approximately the same plane, or if some of the contacts on the wafer are out of plane, more force must be exerted on the back of the probe in an effort to engage all of the probe contacts with the chip contacts. This typically leads to nonuniform forces between the tips of the probe contacts and the wafer contacts. If too much force is placed on any one probe contact, there is a potential to harm the chip contacts. Planarity and a balanced probe contact force is also important in order to have approximately the same ohmic resistance across all of the probe contacts so that the electrical signals have approximately the same level of integrity. Maintaining similar ohmic probe to chip contact resistance is especially important for accurate testing of chips that are designed to be run at high speeds. For such high speed chips, it is also important to control the impedance of the probe tester (resistance, capacitance and inductance) as a whole to maintain the integrity of the electrical signals.
U.S. Pat. No. 4,566,184 discloses a probe card that has a board with an aperture in it. The board has conductive traces on a top surface. A bottom surface of the board has a conductive layer which is used as a ground layer. The conductive traces are connected to electroplated probe contacts that are located below the board aperture and connected to the traces by way of wire bonded connections. The assembly is encapsulated (such as by an acrylic potting compound) in order to hold the probe contacts in place and protect the wire bonds. The wire bonded wires connecting the probe board to the contacts provide an uncontrolled impedance paths that will introduce added inductance into the probe system. Also, because of the limitations inherent with such wire bonded connections, it would be difficult to make connections to high density chip contacts and area array chip contacts without substantial fear that the wires would short against each other.
U.S. Pat. Nos. 4,757,256 and 4,837,622 disclose a probe tester that makes use of an array of cantilevered, resilient wires each of which extends from the surface of the probe card downwardly towards the chip contacts. The probe contact array includes an annular frame, and two sets of spaced apart probe wires bonded to the annular frame by a curable resin material. The probes are bonded in alignment position relative to respective connection pads formed on each of the chips on the wafer for individual testing of chips on an undiced wafer. The adjacent probe wires of both sets are substantially parallel with each other, one set of probe wires being spaced apart from the other set. One set of probes is adapted for electrical connection to the first set of traces on the lower surface, and the other set of probes is adapted for electrical connection to the second set of traces on the upper surface of the printed circuit probe card, in all cases by way of the lower surface thereof. This type of probe card had difficulty when the center-to-center distance (xe2x80x9cpitchxe2x80x9d) of the chip contacts becomes fairly small or when the contacts are not located on a periphery of the chip itself. Also, the distended wires may cause excessive scrubbing of the chip contacts and shorting of adjacent probe wires during testing or handling of the probe card. U.S. Pat. No. 5,613,861 discloses a spring contact probe that eliminates the need to create uniform solder bumps or uniform contacting pressure. The spring contacts are formed of a thin metal strip which is in part fixed to a substrate and electrically connected to a contact pad on the substrate. The free portion of the metal strip not fixed to the substrate bends up and away from the substrate because of a stress gradient formed into it. When the contact pad on a device is brought into pressing contact with the free portion of the metal strip, the free portion deforms and provides compliant contact with the contact pad. Since the metal strip is electrically conductive or coated with a conductive material, the contact pad on the substrate is electrically connected to the contact pad on the device via the spring contact.
U.S. Pat. No. 5,177,439 discloses an interface probe card for testing unencapsulated semiconductor devices. The probe card is manufactured from a semiconductor substrate material. A plurality of protrusions is formed in the top surface of the substrate. Each protrusion is coated with a layer of conducting material. The protrusions are patterned to match either a peripheral or an area array of electrode pads on the device to be tested. Conductive interconnects couple each of the plurality of coated protrusions to an external test system. The probe card design disclosed in this patent has the benefit of using semiconductor type equipment for its manufacture but makes a somewhat rigid connection during a probe operation.
U.S. Pat. No. 5,513,430 discloses a method for manufacturing a probe card. A layer of resist is formed on a plating base. The layer of resist is exposed to radiation and developed to provide angled, tapered openings exposing portions of the plating base, such as by using x-ray radiation. An electrically conductive material is electroplated on the exposed portions of the plating base and fills the angled, tapered openings. The layer of resist and portions of the plating base between the electroplated conductive material are removed. The electrically conductive material forms the probe card probes which are angled and tapered. In addition, the compliant probe card probes may be stair-step shaped if more conventional UV radiation is used in defining the tapered openings in the plating base..
U.S. Pat. No. 5,070,297 discloses a wafer level probe tester where all of the chips are tested simultaneously prior to a dicing operation. The disclosed probe tester is created using standard wafer processing techniques to embed active testing and interfacing circuitry in the probe""s base silicon substrate. Each probe tester has a plurality of probe contacts or tips that are electrically connected to the probe tester""s circuitry. In this disclosure, probe tester may also have memory for storing the probe data after the probe tester has probed a wafer. While the ability to have internal circuitry in the probe tester potentially increases the ability to test the chips in the wafer at higher speeds, it has the drawback of requiring extra processing of the tester""s base substrate. As more and more circuitry is added across the face of the tester""s base substrate, the probe tester encounters the same problems encountered in the field with wafer-scale integration techniques, namely the yield of the circuitry within the base substrate will be adversely affected as more circuitry is added to the base substrate. The problem usually occurs when very high yielding circuitry is used with lower yielding circuitry. The aggregate yield of the resulting circuitry is never any higher than the lowest yielding circuitry, leading to a more expensive process and structure.
Bumped flex test technology has been used by several manufacturers (also known as xe2x80x9cmembrane probe card technologyxe2x80x9d). Test circuits are created on a membrane, such as a thin flexible polymeric substrate or silicon substrate. Typically such test circuits are limited to diameters of approximately 3 inches and incorporate bump contact feature sizes of 50 microns minimum line and space. Such feature sizes are necessary to access the I/O lands of the IC device. Such contact bumps can be as small as 50 microns in both diameter and height. The simplest method of creating the contact bumps is by deforming the metal from the back side by use of a forming die consisting of pins that are located where the contact bumps are to be located. This method works very effectively but is limited in terms of minimum size of the bump that can be produced and in terms of performance because the cavity created during the bump formation can be a source of weakness. In addition, such contact bumps normally must be over plated after the forming process with a suitable contact finish such as gold. This is not only cumbersome but can add to whatever non-planarity that was present in the part initially. Another method used for creating the bumps, especially micro-bumps or metal contact bumps having dimensions of less than 250 microns across and rising 25 to 100 microns above the surface, is to uniformly plate up the bumps from the surface of the conductor. This has been performed by several manufacturers and is the method of choice for creating uniform contact bumps. These methods for creating a membrane probe card have been seen as either cost prohibitive or have been viewed as impractical for testing of printed circuit boards (xe2x80x9cPCBsxe2x80x9d). This is due perhaps to the intrinsically high cost of the test circuits and the small and delicate nature of the test circuits. Another membrane probe tester for testing unpackaged chips having flip chip solder balls attached to their contacts is shown in U.S. Pat. No. 5,062,203 (xe2x80x9c""203 patentxe2x80x9d). The ""203 patent does not make use of the aforementioned bump contacts because they can deform or damage the flip chip solder balls on the chip""s contacts and typically have a difficult time maintaining contact with the solder ball""s curved surface. Instead, this reference uses a thin film of flexible material having recessed conductive vias so that the tips of each solder ball can be captured therein. Other flex based probe card solutions are disclosed in U.S. Pat. Nos. 5,123,850; 5,225,037; 5,436,568; 5,491,427; 5,500,604; 5,623,213; 5,625,298; 5,239,260.
The technology disclosed in commonly assigned U.S. Pat. Nos. 5,148,265; 5,148,266; 5,414,298; 5,455,390; 5,518,964; and 5,525,545 is also relevant to the present invention. The disclosures in all such recited commonly assigned patents are hereby incorporated by reference herein.
Notwithstanding the positive results of the aforementioned commonly owned inventions, still further improvements would be desirable.
One aspect of the present invention provides methods of making probe cards. Preferred methods according to this aspect of the present invention include the step of providing a sacrificial layer, a substrate having electrical circuits thereon and a plurality of elongated leads. Each lead has a first end connected to the sacrificial layer and a second end attached to the substrate and connected to the circuits thereon. The first ends of at least some of the leads are physically connected to the first ends of others of the leads by the sacrificial layer. The method further includes the step of moving the substrate and the sacrificial layer away from one another so as to bend the second ends of the leads away from the sacrificial layer while leaving the first ends of the leads in position on the sacrificial layer. Preferably a flowable material is injected around the leads during or after the moving step and cured so as to form a dielectric encapsulant layer surrounding the leads. The sacrificial layer typically is removed by dissolving or eroding the layer.
In one preferred embodiment, the step of providing the sacrificial layer includes the step of providing the sacrificial layer with electrically conductive terminals at a bottom surface of the layer. These terminals are connected to the first ends of the leads. The sacrificial layer protects these terminals from the flowable material during injection of the flowable material. Desirably, the step of providing the terminals includes the step of forming the terminals on the sacrificial as, for example, by placing electrically conductive material into cavities in the sacrificial layer so that the terminals project upwardly from the bottom surface of the sacrificial layer. In this arrangement, the terminals will project above the encapsulant layer when the sacrificial layer is removed. Desirably, the sacrificial layer is provided with the leads thereon, and the leads may be integral with the terminals. For example, the leads and the terminals may be formed in a single metal-depositing step. The cavities in the sacrificial layer may include sharp features so that the electrically conductive material deposited into the cavities forms a short feature such as points on the terminals.
The leads may be formed solely from one or more metals, as, for example, from metals such as gold, copper or combinations thereof. The terminals may include the aforesaid conductive metals and may also include one or more hard metals such as osmium, rhodium and the like. The leads may include polymeric strips as well as conductive strips.
The encapsulant layer may be a compliant material. Also, the method may further include the step of forming channels in the encapsulant layer so as to subdivide the encapsulant layer into different portions of the encapsulant layer surrounding different ones of the leads. This facilitates movement of leads and terminals associated with different portions of the encapsulant independent of one another, and makes it easier for the terminals to conform to the contact pads on the electronic element.
Further aspects of the invention provide probe cards for testing electronic elements. A probe card in accordance with this aspect of the invention desirably includes a substrate having electrical circuitry thereon, an encapsulant layer overlying the substrate and a plurality of flexible leads extending through the encapsulant layer. Desirably, the terminal project above the encapsulant layer and are exposed for engagement with contact pads on an electronic element such as semiconductor device. The terminals desirably have sharp features such as points or edges for engaging the contact pads on the electronic element. Also, the encapsulant layer desirably has channels therein subdividing the encapsulant layer into portions associated with the different leads. For example, a single lead, or a few leads, maybe provided within each portion. The various portions of the encapsulant layer desirably are deformable independently one of one another. The terminals maybe physically connected to one another solely by the encapsulant layer, leads and substrate. Alternatively, the probe card may include a flexible dielectric layer overlying the encapsulant layer, the electric layer having a top surface facing away from the encapsulant layer and substrate. In this embodiment, the terminals may be attached to the flexible dielectric layer and may protrude therethrough so that the terminals are project above the top surface of the flexible dielectric layer.
Yet another aspect of the present invention provides methods of testing electronic elements. A method according to this aspect of the invention includes the step of providing a probe incorporating a substrate with electrical circuitry, an encapsulant layer overlying a surface of the substrate and leads extending upwardly from the substrate through the encapsulant layer, the leads having terminals remote from the substrate projecting from the encapsulant layer, and temporarily engaging the terminals of the probe with contact pads on the electronic element by urging the substrate and electronic element towards one another so as to deform the leads and the encapsulant layer.
While the terminals are engaged with the contact pads, the electronic device is actuated so that signals are sent between the electronic element and the circuitry on the substrate through the engaged contact pads and terminals and through the leads. The electronic element maybe a relatively large element such as a printed wiring board or semiconductor device such as a wafer, including a multiplicity of semiconductor chips, each having contact pads. In the latter case, the terminals of the probe maybe simultaneously engaged with the contact pads of a plurality of the chips in the wafer. Most preferably, the terminals of the probe are simultaneously engaged with the contact pads with all of the chips in the wafer. Stated another way, the preferred methods according to this aspect of the invention provide the capability of conducting a true wafer-level test.
The probe card can be fabricated with leads and terminals, the terminals being connected at a close terminal to terminal spacing or xe2x80x9cpitchxe2x80x9d corresponding to the pitch of the contact pads on a wafer. Moreover, as further discussed below, the locations of the terminals can be controlled precisely during fabrication of the probe card. Also, the probe card can be fabricated in a relatively large size comparable to the size of an entire wafer or the size of an entire printed wiring board. These and other objects, features and advantages of the present invention will be more readily apparent from the detailed description of the preferred embodiments set forth below, taken in conjunction with the accompanying drawings.
In its preferred forms, the present invention provides a novel, yet inexpensive probe card for the testing of single chips, full undiced wafers or other electronic components. The resulting probe card structure allows the probe card terminals to be located anywhere thereby allowing the testing of chips that have peripherally located chip contacts, area array chip contacts or non-uniformly arranged chip contacts, as well as wafers incorporating such chips.